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	SCHEDULE: NOV 11-17, 2006 Toward a Power Efficient Computer Architecture for Barnes-Hut N-Body Simulations Session: Poster Reception Event Type: Poster Time: 5:15pm - 7:15pm Author(s): Konrad Malkowski, Padma Raghavan, Mary Jane Irwin Location: Ballroom Corridor Abstract: Recent improvements in processor performance have been accompanied by increased chip complexity and power consumption, resulting in increased heat dissipation. This has resulted in higher cooling costs and lower reliability. In this paper, we focus on power-aware high performance scientific computing and in particular the Barnes-Hut (BH) code that is used for N-body problems. We show how low power modes of the CPU and caches, and hardware optimizations such as a load miss predictor and data prefetchers enable BH to operate at lower power configurations with out performance degradation. On our optimized processor, power is reduced by 57% and energy is reduced by 58% with no performance penalty using simulations with SimpleScalar and Wattch. Consequently, the energy efficiency of the processor increases by a factor of more than two when compared to the base architecture. Chair/Author Details: Konrad Malkowski Pennsylvania State University Padma Raghavan Pennsylvania State University Mary Jane Irwin Pennsylvania State University
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