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	SCHEDULE: NOV 11-17, 2006 IANUS: Scientific Computing on an FPGA-based Architecture Session: Poster Reception Event Type: Poster Time: 5:15pm - 7:15pm Author(s): Filippo Mantovani Location: Ballroom Corridor Abstract: IANUS is a massively parallel system based on a 2D array of FPGA-based processors with nearest-neighbor connections. Processors are also directly connected to a central hub attached to a host computer. The prototype, available in October 2006 uses an array of 4x4 Xilinx Virtex4LX160 FPGA's. We map onto the array the computational kernels of scientific applications characterized by regular control flow, unconventional mix of data-manipulation operations and limited memory usage. Careful VHDL coding of the kernel algorithms relevant for Monte Carlo simulation of spin-glass systems (our first application) yields impressive performances: single processor tests concurrently update ~1000 spins, so average spin-update time is 15 psec. This is ~60 times faster than accurately programmed 3,2 GHz PC's. We plan to build a 256 nodes system, roughly equivalent to 15000 PC's. This poster describes the architecture, the implementation and the methodology with which a specific application is mapped onto the system. Chair/Author Details: Filippo Mantovani University of Ferrara
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