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	SCHEDULE: NOV 11-17, 2006 Beyond the Beyond and the Extremes of Computing Session: Computer Science - Architecture Event Type: Masterwork Time: 4:15pm - 5:00pm Speaker(s): Thomas Sterling Location: Ballroom A Abstract: Twenty five years ago supercomputing was dominated by vector processors and emergent SIMD array processors clocked at tens of Megahertz. Today responding to dramatic advances in semiconductor device fabrication technologies, the world of supercomputing is dominated by multi-core based MPP and commodity cluster systems clocked at Gigahertz. Twenty five years in the future, the technology landscape will again have experienced dramatic change with the flat-lining of Moore's Law, the realization of nanoscale devices, and the emergence of potentially alien technologies, architectures, and paradigms. If Moore's Law were to continue to progress as before, we would be deploying systems approaching 100 Exaflops with clock rates nearing a Terahertz. But by then, power constraints, quantum effects, or our inability to exploit trillion way program parallelism may have forced us in to entirely new realms of processing. This presentation will consider the range of alternative technologies, architectures, and methods that may drive the extremes of computing beyond the current incremental steps of the current era. Chair/ Speaker Details: Thomas Sterling Louisiana State University Dr. Thomas Sterling is a Professor of Computer Science at Louisiana State University, a Faculty Associate at California Institute of Technology, and a Distinguished Visiting Scientist at Oak Ridge National Laboratory. He received his PhD as a Hertz Fellow from MIT in 1984. Dr. Sterling is probably best known as the "father" of Beowulf clusters and for his research on Petaflops computing architecture. He was one of several researchers to receive the Gordon Bell Prize for this work on Beowulf 1997. In 1996, he started the inter-disciplinary HTMT project to conduct a detailed point design study of an innovative Petaflops architecture. He currently leads the MIND memory accelerator architecture project for scalable data-intensive computing and is an investigator on the DOE sponsored Fast-OS Project to develop a new generation of configurable light-weight parallel runtime software system. Thomas is co-author of five books and holds six patents.
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